Overview
Skills
Job Details
Job Title: Design Verification Engineer
Location: Sunnyvale, CA / Redmond, WA / Austin, TX
Work Type: Full-Time, Onsite (Hybrid No Remote Allowed)
Employment Type: Permanent (No Contractors)
Experience Range: 7 to 18 Years (No profiles with over 18 years of experience)
Key Responsibilities:
- Develop and maintain UVM/SystemVerilog-based verification environments for IP, subsystem, and SoC level.
- Understand design specifications and architectural documents to create effective test plans.
- Write and execute both directed and random testcases.
- Perform functional and code coverage analysis and work towards closure.
- Debug simulation failures, analyze root causes, and work closely with RTL design teams.
- Execute and manage regression test runs; analyze results and drive improvements.
- Run power-aware simulations, perform low-power verification with UPF/CPF.
- Collaborate with cross-functional teams including DFT, PD, RTL, and post-silicon validation.
- Ensure high quality and completeness of verification activities across various design stages.
- Document test environments, test plans, and results for both internal and external stakeholders.
Required Skills:
Strong expertise in SystemVerilog (SV) and UVM methodologies.
Solid understanding of AMBA protocols (AXI/AHB/APB).
Proven debugging and problem-solving skills in simulation environments.
Hands-on experience with industry-standard EDA tools and simulators.
Familiarity with low-power design methodologies and verification flows.
This is an excellent opportunity to join a cutting-edge semiconductor team working on high-impact, next-gen SoC designs.
Note: This is a hybrid onsite role. Remote work is not allowed.