FPGA Validation Engineer

Role: FPGA Validation Engineer

Location: Santa Clara, CA (Onsite)

Skills: VHDL, Verilog, Hardware Description Languages (HDL), UVM (Universal Verification Methodology) and OVM (Open Verification Methodology), DSP, Python and TCL, Xilinx (Vivado) and Intel (Quartus)

Roles & Responsibilities:

• Validating and implementing digital circuits using FPGA technology
• Testing and debugging designs to ensure they meet requirements
• Collaborating with other engineers and stakeholders to ensure designs meet project goals
• Staying up to date with the latest developments in FPGA technology and incorporating them into designs

Experience:

5 to 8 years of experience

• Experienced in Verilog and VHDL proficiency, FPGA synthesis tools (Xilinx Vivado, Intel Quartus).
• Signal processing algorithms and Embedded systems programming.
• Deep understanding of digital logic design and computer architecture
• FPGA simulation tools (Model Sim, VCS).
• High speed communication protocols validation (e.g., DDR, HDMI, PCIe, Ethernet).
• FPGA verification methodologies
• Test case coding in Verilog/ System Verilog.
• Simulation Environment development and maintenance.
• Code Coverage analysis
• Assertions development and Assertion Based Verification
• Development of software models in high level languages like Python, C

Support the development team in hardware debugging