Senior ASIC/RTL Design Engineer

Overview

On Site
$$74.78hr - $78.78hr
Contract - W2
Contract - to 2026-06-14

Skills

ASIC/RTL Design Engineer

Job Details

Job Description:
Pay Range: $74.78hr - $78.78hr
Responsibilities:
  • Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
  • CollaboXX with architecture and hardware teams to understand the requirements.
  • Work with verification and physical design teams to achieve high quality design and successful tape out.
  • XXgn and implement logic functions that enable efficient test and debug.
  • Participate in silicon bring-up for features owned.
  • Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features.
  • Implement automation to increase design team efficiency.
Experience Required:
  • 5-6+ years' experience required.
  • Must have proven track record of ASIC design on several production tape-outs.
  • Experience in XXgning RTL block for an SOC.
  • Experience in integrating ASIC IP into an SOC.
  • Experience with synthesis, static timing analysis & optimizations.
Nice-to-Have:
  • Experience writing timing constraints and exceptions.
  • Experience with automation using scripting techniques such as PERL, Python or Tcl
  • Experience in Power-saving techniques.
  • Experience with Arm architecture and APB, AXI, CHI protocols.
  • Experience with design involving Interconnects.
  • Ability to develop clear and concise engineering documentation.
  • Ability to organize and present complex technical information.
  • Strong verbal and written communication skills
Education:
  • Bachelor's degree required
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