Overview
On Site
$60,000 - $80,000
Full Time
Skills
Verilog
VHDL
SystemVerilog
: RTL/FPGA
TCL
Python
Job Details
- Design & Implementation: Develop RTL code (Verilog, VHDL, SystemVerilog) for FPGA and digital circuits, integrating IP and system software.
Simulation & Debugging: Perform functional simulation, debug FPGA designs, and resolve design issues.
Validation & Testing: Create unit tests, example designs, and demos; ensure readiness of feature releases.
Technical Enablement: Develop user guides, application notes, and training materials for customers.
Customer Support: Respond to technical inquiries, reproduce issues, and collaborate with engineering teams for resolution.
Optimization: Conduct synthesis, power, and thermal analysis to meet performance and efficiency targets.
Collaboration: Work closely with architecture, verification, and physical design teams to deliver high-quality solutions.
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