Silicon Digital Design Engineer

Overview

On Site
$97.04 - $109.32 hr
Contract - Independent
Contract - W2
Contract - 5+ mo(s)

Skills

ASIC
SOC
RTL
SYSTEMVERILOG
VERILOG
UVM
UPF
UNIFIED POWER FORMAT
SYNTHESIS
STA

Job Details

Payrate: $97.04 - $109.32/hr.

Summary:
We are seeking a talented and driven Silicon Digital Design Engineer to join our team. In this role, you will be responsible for the architecture, design, integration, and verification of advanced ASIC and SoC solutions. You will collaborate with cross-functional teams to deliver high-performance silicon products from concept to production.

Responsibilities:
  • Develop efficient digital microarchitectures and contribute to ASIC digital architecture, design, and verification.
  • Integrate IPs and drive top-level microarchitecture definition and RTL development.
  • Lead chip-level integration, verification plan development, and execution.
  • Supervise the RTL-to-GDS flow, including synthesis and timing closure.
  • Support test program development, chip validation, and product maturity.
  • Collaborate with FPGA engineers for early prototyping and validation.
  • Assist with algorithm analysis, verification, and improvement.
  • Support hand-off and integration of blocks into larger SoC environments.
  • Apply Design for Verification concepts throughout the design process.

Must-Have Qualifications:
  • 4+ years of experience as a Digital Design Engineer and/or Chip Lead.
  • Strong experience in RTL coding, synthesis, and/or SoC integration.
  • Solid background in digital design microarchitecture.
  • Proficiency with Verilog and SystemVerilog coding.
  • Bachelor s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • Experience with UPF-based simulation flow.
  • SystemVerilog OVM/UVM experience.
  • Scripting experience with Tcl and Python (or similar).
  • Experience in SoC integration and ASIC architecture.

Nice-to-Have Qualifications:
  • Experience with DFT/Testability requirements and test program definition.
  • Familiarity with high-speed interfaces (PCIe, USB, MIPI).
  • FPGA design experience.
  • Knowledge of Tensilica DSP, TIE, CNN, fixed point, floating point, and Python.
  • Experience with Power Aware GLS flow.
  • Master s degree in Electrical/Computer Engineering or Computer Science.

Pay Transparency: The typical base pay for this role across the U.S. is: $97.04 - $109.32/hr. Final offer amounts, within the base pay set forth above, are determined by factors including your relevant skills, education and experience and the benefits package you select. Full-time employees are eligible to select from different benefits packages. Packages may include medical, dental, and vision benefits, 10 paid days off, 401(k) plan participation, commuter benefits and life and disability insurance.

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