UVM Digital Verification Engineer

Job Description Summary:

Draper s Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.

Job Description:

Duties/Responsibilities

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• Design and simulate circuits at transistor-level to implement architecture and requirement specifications
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• Contribute to system-level design
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• Optimize hardware designs for performance, power, and cost
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• Evaluate the hardware feasibility of complex algorithms and requirements
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• Independently contribute to complex chip architectures and designs
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• Independently drive solutions to complex problems - develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements
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• Contribute to business development and proposal activities
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• Develop, document, and teach best practices to less experienced engineers
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• Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics.
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• Perform other duties as assigned
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Skills/Abilities

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• Proficiency in integrated circuit design
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• Understanding of integrated circuits, semiconductors, and general computer architecture
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• Ability to write detailed design specifications
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• Ability to manage small technical teams
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• Excellent verbal and written communication skills
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• Excellent mathematical skills
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• Excellent organizational skills and attention to detail
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• Excellent time management skills with the proven ability to meet deadlines
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• Strong analytical and problem-solving skills
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• Ability to prioritize tasks
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• Demonstrate strong organization, planning, and time management skills to achieve program goals
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Education

• Requires a bachelor's degree in Engineering, or related field. Masters degree preferred.

Experience

• Requires 5-7 years of experience with a bachelor's degree, or 3-5 years of experience with a master's degree, or 0-2 years of experience with a PhD in ASIC Hardware Engineering or related.

Additional Job Description:

You will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.

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• Develop verification and test plans
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• Develop UVM Agents for proprietary buses
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• Instantiate VIPs for industry standard buses
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• Work in both block-level/chip-level UVM testbench environment
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• Work with RTL designers to resolve simulation issues
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• Implement cover groups according to design requirements
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• Work on code and functional coverage closures to achieve 100%
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• Perform code reviews and to mentor junior engineers in the group
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• Fluent in System Verilog including SVA
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• Recent experience with UVM/UVMF
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• Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS)
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• Familiarity with at least one IEEE bus standard Experience with DDR3/DDR4, Amba Axi protocols
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• Firm grasp of constrained-random testing and coverage-driven verification
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• Experience with formal analysis
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• Practice using Python, Perl, Bash or other scripting languages
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• Ability to work in a Linux environment
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• Strong analysis and problem-solving skills
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Applicants selected for this position will have or be able to obtain and maintain a government security clearance.