CPU Physical Design Pathfinding Engineer

Overview

On Site
$317000
Full Time

Job Details

Overview

Lead cross-functional efforts to develop next-gen CPU technologies that meet aggressive Power, Performance, and Area (PPA) goals. Collaborate with Architecture, RTL, Physical Design, Circuits, CAD, and Post-Silicon teams to drive innovation and optimization.

Key Responsibilities

  • Solve critical CPU implementation challenges across design and CAD teams.
  • Develop and apply advanced physical design and optimization techniques.
  • Align CPU design strategies with real-world use cases and system requirements.
  • Enhance design flows in collaboration with internal and external tool teams.
  • Support pre- and post-silicon analysis and correlation.

Required Skills

  • Strong background in synthesis, place & route, and timing/power signoff.
  • Expertise in high-performance, low-power design.
  • Proficient in TCL, Python, and Perl scripting.

Preferred Qualifications

  • MS in Electrical Engineering with 14+ years of experience.
  • Experience with deep submicron nodes and CPU PPA optimization.
  • Familiarity with library cell design, EDA tools, and tapeout flows.
  • Strong analytical and debugging skills.

Minimum Education & Experience

  • BS + 8 years, MS + 7 years, or PhD + 6 years in EE, CE, CS, or related field.

 

Determining compensation for this role (and others) at Vaco/Highspring depends upon a wide array of factors including but not limited to the individual’s skill sets, experience and training, licensure and certifications, office location and other geographic considerations, as well as other business and organizational needs. With that said, as required by local law in geographies that require salary range disclosure, Vaco/Highspring notes the salary range for the role is noted in this job posting. The individual may also be eligible for discretionary bonuses, and can participate in medical, dental, and vision benefits as well as the company’s 401(k) retirement plan.

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