10112463

<!DOCTYPE html><html><head></head><body><pre>Job Title: Chip Desgner/Packaging<br /><br />Job Location: Santa Clara, CA (Hybrid)<br /> </pre><div class="dragbox-content"><div><div id="descriptiondiv"><div><ul><li><strong>IC Packaging & Chiplet Integration </strong>: 2.5D/3D packaging, flip-chip bonding, TSV, hybrid bonding</li><li><strong>Semiconductor Processing </strong>: BEOL/FEOL integration, advanced interconnects, thin-film deposition (PVD, PECVD, ALD, CVD)</li><li><strong>Design & Simulation </strong>: <strong>Siemens NX, Cadence, ANSYS, EasyEDA, ThermoCalc</strong></li><li><strong>High-Speed I/O & Signal Integrity </strong>: Impedance control, power/signal integrity, substrate optimization</li><li><strong>Process Development & Metrology </strong>: DOE, SPC, FMEA, SEM, TEM, AFM, Raman spectroscopy</li><li><strong>Cross-Functional Collaboration </strong>: Foundry/OSAT coordination, ASIC design support, product lifecycle management</li></ul></div></div></div></div><div id="jobScheduleDiv" class="dragbox"><pre class="drag-bar"> </pre></div></body></html>

(CHIPLET PACK OR CHIPLET PACKAGING OR CHIP PACK OR CHIPLET PACKAGING OR CHIPLET OR CHIP) AND ("CADENCE" OR "ANSYS" OR "SIEMENS NX") AND ("FMEA" OR "SPC" OR "DOE")

Chip Desgner/Packaging

Job Details

Share