ASIC Engineer

Role: ASIC Engineer

Location: Clara CA 95054 OR Longmont CO 80503

Duration: 12+months

Job Description:

• Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
• Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
• Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)
• Constantly review/identify the places to improve the process and ways to identify the issues early in the design phase.
• Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency.
• Attention to the detail. Very good communication skills (both written and verbal)
• Fast learner and self-starter. Need to execute our custom regression scripts/quality checks for our complex designs (Multimode, multimillion gates and multiple partitions)
• Understand the PT/DC checks and review the reports to help clean up in order to meet each milestone targets.
• Summarize the regression results periodically to track the progress.

Preferred experience:

• Minimum of 6-8 years' experience
• Worked with EDA tools that enable RTL quality checks
• Experience with analyzing the timing reports and identifying both the design and constraints related issues.
• Ability to multitask, ramp up quickly on new flows/tools/ideas.
• Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable