Overview
On Site
USD 143,200.00 - 214,500.00 per year
Full Time
Skills
Semiconductors
Cloud Computing
Artificial Intelligence
Innovation
Regulatory Compliance
Physical Layer
Expect
Reporting
Test Plans
Unit Testing
Firmware
Storage
Serial ATA
SAS
Ethernet
Computer Hardware
Oscilloscope
Computer Science
Electrical Engineering
IO
Testing
System Testing
Debugging
Test Equipment
BERT
Network
Analytical Skill
Problem Solving
Conflict Resolution
Communication
PCI Express
Interfaces
PCB
Schematics
Layout
SERDES
Modeling
Perl
Python
Finance
Help Desk
IBM Cognos TM1
Job Details
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a Hardware and Silicon Validation Principal Engineer at Marvell, you'll be helping to deliver high quality products. This team performs system level and functional validations on post silicon products that drive optical electronic devices and receivers. We also conduct interop and compliance tests on physical layer, link layer and transaction layer, working with cutting edge technologies used by many internal and external customers around the world.
What You Can Expect
Complete responsibility for PCIe PHY Validation in post-silicon environment.
Defining, documenting, executing and reporting the overall PHY validation/test plan for Marvell storage devices
Lab-based silicon bring-up and unit test execution focused on PCIe Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack.
Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER.
Analyze and debug issues on Phy protocol of storage interface ( SATA, SAS, PCIe, Ethernet )
Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers.
Leading collaborative technical discussions to drive resolution on technical issues Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe PHY.
Work closely with customers to address design issue and debug failure cases
What We're Looking For
Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience.
Strong understanding of high-speed SERDES, equalization technique and PCIe protocols.
5+ years experience with High Speed IO testing, debugging and validation
Strong lab skills with hands on experience, in system bring up, system testing and debug.
In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.).
Strong analytical, problem-solving and communication skills
Preferred/Plus:
Working knowledge of PCIe interface and characterization.
Working knowledge and experience on PCIe Gen6 and retimer is a definite plus.
Extensive knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is an asset.
Working knowledge of board design; able to read board schematics and board layout.
Knowledge in SERDES modeling techniques Working experience with Perl or Python
Expected Base Pay Range (USD)
143,200 - 214,500, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
#LI-TM1
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a Hardware and Silicon Validation Principal Engineer at Marvell, you'll be helping to deliver high quality products. This team performs system level and functional validations on post silicon products that drive optical electronic devices and receivers. We also conduct interop and compliance tests on physical layer, link layer and transaction layer, working with cutting edge technologies used by many internal and external customers around the world.
What You Can Expect
Complete responsibility for PCIe PHY Validation in post-silicon environment.
Defining, documenting, executing and reporting the overall PHY validation/test plan for Marvell storage devices
Lab-based silicon bring-up and unit test execution focused on PCIe Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack.
Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER.
Analyze and debug issues on Phy protocol of storage interface ( SATA, SAS, PCIe, Ethernet )
Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers.
Leading collaborative technical discussions to drive resolution on technical issues Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe PHY.
Work closely with customers to address design issue and debug failure cases
What We're Looking For
Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience.
Strong understanding of high-speed SERDES, equalization technique and PCIe protocols.
5+ years experience with High Speed IO testing, debugging and validation
Strong lab skills with hands on experience, in system bring up, system testing and debug.
In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.).
Strong analytical, problem-solving and communication skills
Preferred/Plus:
Working knowledge of PCIe interface and characterization.
Working knowledge and experience on PCIe Gen6 and retimer is a definite plus.
Extensive knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is an asset.
Working knowledge of board design; able to read board schematics and board layout.
Knowledge in SERDES modeling techniques Working experience with Perl or Python
Expected Base Pay Range (USD)
143,200 - 214,500, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
#LI-TM1
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.