RTL Design Engineer || Santa Clara, CA || HYBRID

Overview

On Site
Accepts corp to corp applications
Contract - W2
Contract - Independent
Contract - 8 month(s)

Skills

Management
Employment Authorization
SAP MM
LinkedIn
IPS
SERDES
System On A Chip
RTL
Change Data Capture
PCI Express
Ethernet

Job Details

Greetings from Infobahn SoftWorld !!

We have an immediate opportunity with one of our direct clients. Please find the job description below and if you are interested, please share below details:

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Title: RTL Design Engineer

Location: 2485 Augustine Drive, Santa Clara, CA - Hybrid

Duration: 1 Year contract

Must be able to come onsite 3 days per week

JOB DUTIES:

This is a position for principal level RTL design engineer.

As a part of the design team, candidate will be exposed to several IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design.

Successful candidates will be participating in the design of leading edge I/O SoCs in sub- 7 nm processes.

RTL Design Engineers is expected to contribute in all aspects of SoC design including: subsystem definition, Development of micro-architectural specifications, strong RTL design, module level verification, Lint & CDC.

Having experience is Gbit high frequency design such as PCIe & Ethernet Phy design is a big plus.

Candidate must have a BS in EE or CS. MS is a plus.

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