Static Timing Analysis Engineer

Title: Static Timing Analysis Engineer
Location: San Jose, CA
Duration: One Year Plus - Onsite
PR Range: $65 - $70 /hr on W2 or $72 - $75 on C2C. Employee benefits
include, but are not limited to, health insurance (medical, dental,
vision), 401(k) plan, and paid sick leave (depending on work location).

Job Description:
We are looking for a Static Timing Analysis Engineer with atleast 8
years of experience in Functional and test timing constraints, Static
Timing Analysis, Primetime , RTL Coding and Lint Checking, Synthesis
tool exp: Genus (Cadence) and Fusion compiler/design compiler(Synopsis),

What will you do:

Deliver on Static Timing Analysis domain with activities such as Timing
Constraint Development/Modification, Running Chip level and Block level
functional and Test level Static Timing Analysis, analyze and automate
timing fixes.
Primary member of a team responsible for executing project deliverables
and processes necessary to successfully specify, develop, and release to
production highly integrated ASICs.
Skills:
What we are looking for:

Bachelor's degree in electronic engineering, or the equivalent
qualification in training and experience.
8+ yrs of professional engineering experience, including experience in
advanced technology nodes: 28nm, 16nm and below.
Familiar with industry standard CAD methodologies from Cadence,
Synopsys, and/or Mentor.
Successful execution of timing constraint development in previous
projects.
Solid analytical, communication and presentation skills.
Timing Constraint, RTL Coding and lint checking.
Experience with Primetime (Synopsys).
Synthesis tool exp: Genus (Cadence) and Fusion compiler/design
compiler(Synopsis).

Good to have:
Automation.
Good scripting skills with Perl and TCL.
Prior experience in Networking space.