Verification Engineer

  • Longmont, CO
  • Posted 19 hours ago | Updated 19 hours ago

Overview

On Site
$55 - $68
Contract - W2
Contract - 12 month(s)
No Travel Required

Skills

RTLVerification
Verilog
SystemVerilog
ModelSim
VCS

Job Details

Job Description:

Pay Range: $55.17hr - $68.96hr

Requirement/Must Have:
  • RTL verification experience.
  • Experience in Verilog and SystemVerilog.
  • Experience with ModelSim or VCS.
  • Familiarity with UVM verification methodologies and environments.
  • Strong debug skills.
  • Strong analytical skills and attention to detail.
  • Excellent written and communication skills.
Experience:
  • 8 or more years of proven verification experience on Verilog and SystemVerilog for IP development and verification.
  • Experience with simulation tools such as ModelSim or VCS, and VIPs.
  • Familiarity with PCIe and serial protocols is a bonus.
  • client/Xilinx FPGA and tools experience is a bonus.
Responsibilities:
  • Participate in the design and functional verification of a block or blocks of IP.
  • Work as part of a team of design and verification engineers, collaborating with other members to understand and verify the functionality of a design element within the block and overall system.
  • Develop and improve simulation test environments consisting of directed and constrained-random tests to be run during simulation.
  • Adopt evolving verification methodologies used in the industry to functionally verify and work within the existing verification infrastructure.
  • Apply hardware modeling and/or assertion-based verification methods.
  • Contribute to PCIe development and productization, with verification targeting PCIe device testing, DMA, CXL, IDE, VIP models, traffic generators, and checkers.
Should Have:
  • FPGA experience, preferably with Xilinx or client FPGA.
  • Vivado experience.
Skills:
  • RTL verification.
  • Verilog and SystemVerilog.
  • ModelSim or VCS proficiency.
  • UVM methodology knowledge.
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