Principal Signal Integrity Electrical Engineer

Job Description

Oracle's West Coast Hardware Development organization seeks to add a Principal Signal Integrity Electrical Engineer to work with our SI, electrical, mechanical, and power teams in Santa Clara, California!

Here is your opportunity work with ever changing latest unreleased technology from Intel, AMD, Nvidia and other compute, storage, and communications companies to design unparalleled servers for Oracle's Cloud deployments,

database appliance, middleware, and AI solution offerings. Work in a smaller organization within Oracle to team up with other technical experts in Signal Integrity, Power, Electrical, Validation, Mechanical, Diagnostics, BIOS and OS, to leverage their expertise and further enhance your expertise in the field of Signal Integrity using world class SI tools and test equipment.

Build your network with the help and collaboration of 160,000 talented and highly motivated Oracle colleagues, and over 400,000 customers from around the globe. This position focuses on in-house designs! Enjoy the flexibility that allows you to balance your career and personal time while keeping at the leading edge of server technology and designs. The team is responsible for the architecture, analysis, detailed design, development, integration, test, and delivery of Oracle servers based on the latest high-end server-grade merchant silicon. The systems delivered are integrated as building blocks for some of Oracle's market leading and growing Cloud Systems & Appliances. As a Principal Signal Integrity Engineer, you will be responsible for assuring the signal integrity of systems from system conception through system deployment in our cloud data centers. This position is not in an SI service group but rather on a product team with full ownership responsibilities!

Department Description

The Hardware Engineering Organization, within the larger Oracle Hardware Development Organization (OHD), defines and develops the next generation of Oracle hardware platforms and solutions, upon which all of Oracle's Cloud AI, Compute and Storage platforms, are built. These systems utilize leading edge technology to deliver record-breaking performance, simplified management, security, self-monitoring, diagnosis, as well as cost-saving efficiencies. The engineering organization defines, develops, implements, and owns the hardware designs, security lifecycle, and product, from concept through development, integration, introduction to production, and last level support in deployment.

Position Overview:

Our Design Engineering organization is looking for a highly driven, capable, and dedicated Principal Engineer to join the team developing the next generation Servers and AI platforms for the Oracle Cloud.

Career Level - IC4

Responsibilities

The list of responsibilities (but not limited to) may include:

• Work with System architects to assure system designs can meet the leading-edge bus speed requirements of the newest unreleased Intel, AMD, ARM processors, Nvidia GPUs and communication chips.
• Work directly with hardware design and development teams on architecture, implementation, development, deployment, and troubleshooting of SI solutions for Server and AI hardware platforms.
• Evaluate the various design parameters including I/O timing budget, number/type/placement of decoupling capacitors, routing topology - using simulators or measurements from test vehicles.
• Simulate the solution space for High Speed SerDes bus topologies.
• Work with the board designers to arrive at an optimal set of board routing and design rules to ensure optimal noise and timing margin for reliable hardware products.
• Work with Oracle Partners like Intel, AMD and Nvidia to assure server designs meet the Signal Integrity requirements of the silicon.
• Work with Oracle electrical interconnect partners to define high speed low loss interconnect solutions.
• Guide in-house CAD designers to optimally place and route designs for SI.
• Participate in design reviews, system, boards, schematic and board.
• Mentor other SI engineers and Board engineers on good SI practices.
• Critical System component selection including connectors, cables, PCB materials, etc.
• Perform post-layout verification of the signal and power planes on the boards using verification tools.
• Correlate simulation model and result to lab measurements.
• Work with our Validation team to develop and test systems to ensure adequate margin for manufacturability and stability through product lifetime.
• Work in the Lab to debug SI related problems.
• Work with PCB suppliers on stack-up requirements and revisions.

Required Training, Knowledge and Skills:

• Solid electronic circuit background with an in-depth knowledge of modern PCB design techniques for Signal Integrity.
• Strong electromagnetic (EM) or EMI knowledge.
• Must understand the system design trade-offs related to SI.
• In depth knowledge of high-speed design, transmission-line theory, 3D-fieldsolver methods, noise analysis and EMC techniques.
• Experience with simulation tools such as Ansys, ADS, MATLAB, Simbeor, HFSS, Q3D, CST, ADS, Cadence, Sigrity, MATLAB, HSPICE, etc.
• Experience with behavioral models (IBIS or SPICE) and their usage in system level simulation.
• Experience with S-parameters and frequency based analysis.
• Experience with High-Speed PCB laminates and low loss cabling.
• Proficient in constraint driven design methodologies.
• Experience with measurement equipment such as oscilloscope, impedance analyzer, and network analyzer.
• Experience with the board design tools such as Allegro, and Constraint Manager.
• SI design experience with high-speed buses to include: PCIe (Gen5 and above), Intel UPI/DMI, DDR5, SAS, SATA, Muli-gigabit Ethernet (25-100G+), USB, SPI, etc.
• Good communication/presentation skills.
• PhD combined with 3 years of related experience, or MSEE/BSEE combined with 7+ years related experience.

Qualifications

Disclaimer:

Certain US customer or client-facing roles may be required to comply with applicable requirements, such as immunization and occupational health mandates.

Range and benefit information provided in this posting are specific to the stated locations only

US: Hiring Range in USD from: $97,500 to $199,500 per annum. May be eligible for bonus and equity.

Oracle maintains broad salary ranges for its roles in order to account for variations in knowledge, skills, experience, market conditions and locations, as well as reflect Oracle's differing products, industries and lines of business.
Candidates are typically placed into the range based on the preceding factors as well as internal peer equity.

Oracle US offers a comprehensive benefits package which includes the following:
1. Medical, dental, and vision insurance, including expert medical opinion
2. Short term disability and long term disability
3. Life insurance and AD&D
4. Supplemental life insurance (Employee/Spouse/Child)
5. Health care and dependent care Flexible Spending Accounts
6. Pre-tax commuter and parking benefits
7. 401(k) Savings and Investment Plan with company match
8. Paid time off: Flexible Vacation is provided to all eligible employees assigned to a salaried (non-overtime eligible) position. Accrued Vacation is provided to all other employees eligible for vacation benefits. For employees working at least 35 hours per week, the vacation accrual rate is 13 days annually for the first three years of employment and 18 days annually for subsequent years of employment. Vacation accrual is prorated for employees working between 20 and 34 hours per week. Employees working fewer than 20 hours per week are not eligible for vacation.
9. 11 paid holidays
10. Paid sick leave: 72 hours of paid sick leave upon date of hire. Refreshes each calendar year. Unused balance will carry over each year up to a maximum cap of 112 hours.
11. Paid parental leave
12. Adoption assistance
13. Employee Stock Purchase Plan
14. Financial planning and group legal
15. Voluntary benefits including auto, homeowner and pet insurance

The role will generally accept applications for at least three calendar days from the posting date or as long as the job remains posted.

About Us

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