Overview
On Site
Depends on Experience
Contract - Independent
Contract - W2
Contract - 12 Month(s)
Skills
ASIC
Design
Verification
SystemVerilog
UVM
Job Details
Job Title:- ASIC Design Verification Engineer
Duration:-12 months+
Location:-San Jose , CA(Onsite - Work from Office 5 days per week).
About the Role:
We are seeking a highly skilled and motivated ASIC Design Verification Engineer with over 6 years of experience in the field of verification. As an Individual Contributor, he/she will play a crucial role in ensuring the quality and reliability of our cutting-edge ASIC designs, contributing to industry-leading innovations.
Key Responsibilities:
- Develop and implement test plans, test cases, and coverage metrics for ASIC verification.
- Perform block-level and chip-level verification
- Proficiency in SystemVerilog and UVM (Universal Verification Methodology).
- Exposure to CPU-based verification techniques is highly desirable.
- Familiarity with Direct Programming Interfaces (DPI) is a plus.
- Strong problem-solving and debugging skills, with a keen attention to detail.
- End to End
- Full block verification experience
- Digital verification is most important - not looking for analog
Zafar Khan
Technical Recruiter
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