Overview
On Site
Hybrid50 % Onsite 50 % remote
Depends on Experience
Contract - W2
Contract - 6 Month(s)
Skills
CMOS
Cadence Virtuoso
Hardware
Hardware Design
ant
debug
improve memory
layout design
problem - solving
problem - solving skills
teamwork
Calibre
Job Details
Job Description:
- We are seeking a highly skilled and experienced Hardware Design / Custom Memory Layout Engineer to join our team.
- The ideal candidate will have 8 to 10 years of experience in custom memory layout design and must have experience with 5nm and/or 3nm technology nodes.
- In this role, you will be responsible for designing and implementing custom memory layout for advanced technology nodes.
- You will collaborate with circuit designers to optimize memory performance, power, and area.
- You will also perform all physical verification (lvs,drc,ant,etc) and debug of memory layout, and work with the process integration team to ensure manufacturability of memory layout.
- As a Senior Custom Memory Layout Engineer, you will participate in design reviews and provide feedback to improve memory layout quality.
- You will also be expected to stay up-to-date with the latest industry trends and developments in memory layout design.
Requirements:
- 8 to 10 years of experience in custom memory layout design
- Experience with 5nm and/or 3nm technology nodes
- Strong understanding of memory layout techniques and methodologies
- Experience with industry standard layout tools
- Excellent communication and teamwork skills
- Bachelor's or Master's degree in Electrical Engineering or related experience
- The successful candidate will have a strong track record of delivering high-quality memory layout designs and will be able to work independently as well as part of a team.
- You will have excellent problem-solving skills and the ability to think creatively to find innovative solutions to complex challenges.
- This is an exciting opportunity to work on cutting-edge technology and make a significant impact on the industry.
- If you meet the requirements and are interested in this position, please apply with your resume and a cover letter.
- We offer a competitive salary and benefits package, as well as opportunities for career advancement within the company.
- 8-10 years experience required.
Candidate Requirements
- Years of Experience Required: 8-10 overall years of experience in the field.
- Degrees or certifications required: Electrical engineering degree preferred, not required or work experience equivalent.
- Extensive knowledge of deep sub-micron CMOS (FinFet experience is a must, 5nm and below is preferred).
- Experience working with distributed design teams a plus.
- Knowledge of skill code an layout automation a plus.
- Self starter with the ability to define and adhere to a schedule.
- Performance Indicators: Performance will be assessed based on meeting deadlines and quality of work (see JD below).
Top 3 Hard Skills Required + Years of Experience
- 5nm and/or 3nm experience with full custom finfet layout track record (8-10 YOE)
- Use of Cadence Virtuoso and Calibre (8-10 YOE)
- Good verbal, written and presentation skills with analytical and problem-solving ability (8-10 YOE)
Typical Day in the Role
- Purpose of the Team: The purpose of this team is hardware design as they are doing the data center chips.
- Internal / creating hardware. Sponsors' team does the drawing for the circuit staff / they do the physical drawings for the chips. Extra support is needed.
- Typical task breakdown and operating rhythm: The role will consist of 10% meetings, 90% heads down."