SoC Validation Engineer

  • Posted 11 hours ago | Updated 11 hours ago

Overview

Remote
Depends on Experience
Accepts corp to corp applications
Contract - Independent
Contract - W2
Contract - 12 Month(s)
Able to Provide Sponsorship

Skills

System Verilog
SystemVerilog
SoC
UVM
C
ARM
Jasper

Job Details

SOC Verification

Location: 100% Remote
Duration: 12 months

1. General verification expertise
System Verilog
UVM working experience (In the current scenario not much on UVM, but heavily on "C")
Understanding of ARM processor based SOCs, AXI / AHB
Working knowledge of Processor based C tests for SOC verification (test coding, compilation, loading in TB, failure debug)
Strong hands-on work experience of test development, simulation along with usage of popular EDA tools

2. Good debug skills
Check that engineer has done reasonable amount of debug in past projects
Has logical and methodical approach to debug issues / failures
Has used standard tools for debugging, as applicable
Coresight knowledge / debug is an added advantage We have many tests for connectivity using Jasper Gold, need quick debug effort and it is good to have that skill set.

3. Good problem-solving skills
Assess by giving some sample problems to solve online during the interview

4. Specific experience with following is a big advantage
a) dynamic CDC verification
b) clock sweep tests, dynamic frequency scaling
c) verification of complex reset architectures
d) Debugging of above issues in GLS environment

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