Overview
On Site
USD 170,700.00 - 300,200.00 per year
Full Time
Skills
Analog circuits
Timing closure
Problem solving
Decision-making
UI
Static timing analysis
Technologist
Design
Integrated circuit
System on a chip
IP
CMOS
Data
Analytical skill
Communication
Optimization
Software development
Python
Automation
SPICE
Simulation
Compilers
Foundry
Documentation
Specification
Job Details
Summary
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices!In this exciting role, you'll work collaboratively with the PNR , Custom Digital & Analog Design teams, Power & Tech team and our CAD flow developers. Our team works to specify the analysis condition and IP requirements for timing and noise analysis closure methodologies and we provide guidance specific for timing analysis closure to STA CAD flow developers.
Key Qualifications
STA timing closure experience of gate level and transistor level designs in advanced CMOS process. Thorough understanding of STA and methodologies for timing closure, good understanding of noise, cross-talk, OCV effects, and the ability to understand the relationship between those methodologies to provide waiver for ECO violations. Excellent data analytical, problem solving, and communication skills. Experience working with cross-functional teams and driving decision making is highly desired.Understanding of front end timing methodologies and constraints as they relate to backend analysis closure and PPA (power, performance, area) target optimization. Programming experience in Python required.Prior experience delivering new designs to production under a very ambitious schedule ideal. Knowledge of PrimeTime & NanoTime setup/flow automation, Spice simulation and understanding of derates and margins in typical STA/glitch noise closure a bonus. Self-motivated and schedule oriented is a big plus.
Description
- Drive STA and noise methodology working closely with Design, Technology, Power and Architecture teams.- Work with Compiler & Library teams to specify all foundry & third-part IP vendor collateral requirements.- Work with the STA CAD flow developers to incorporate timing closure requirements.- Create documentation and help with guidelines/specs.- Engage parties in decision making and drive to timely closure and thorough follow-through.
Education & Experience
Minimum requirement of BS + 10 years of relevant industry experience.
Pay & Benefits
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices!In this exciting role, you'll work collaboratively with the PNR , Custom Digital & Analog Design teams, Power & Tech team and our CAD flow developers. Our team works to specify the analysis condition and IP requirements for timing and noise analysis closure methodologies and we provide guidance specific for timing analysis closure to STA CAD flow developers.
Key Qualifications
STA timing closure experience of gate level and transistor level designs in advanced CMOS process. Thorough understanding of STA and methodologies for timing closure, good understanding of noise, cross-talk, OCV effects, and the ability to understand the relationship between those methodologies to provide waiver for ECO violations. Excellent data analytical, problem solving, and communication skills. Experience working with cross-functional teams and driving decision making is highly desired.Understanding of front end timing methodologies and constraints as they relate to backend analysis closure and PPA (power, performance, area) target optimization. Programming experience in Python required.Prior experience delivering new designs to production under a very ambitious schedule ideal. Knowledge of PrimeTime & NanoTime setup/flow automation, Spice simulation and understanding of derates and margins in typical STA/glitch noise closure a bonus. Self-motivated and schedule oriented is a big plus.
Description
- Drive STA and noise methodology working closely with Design, Technology, Power and Architecture teams.- Work with Compiler & Library teams to specify all foundry & third-part IP vendor collateral requirements.- Work with the STA CAD flow developers to incorporate timing closure requirements.- Create documentation and help with guidelines/specs.- Engage parties in decision making and drive to timely closure and thorough follow-through.
Education & Experience
Minimum requirement of BS + 10 years of relevant industry experience.
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $170,700 and $300,200, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.