Overview
On Site
$230,000 - $250,000
Full Time
Skills
RTL/Microarchitecture Development
cache design
Cache coherency protocols
RTL Design and Optimization
SoC Integration
On-chip interconnects
Physical Design
Job Details
Requirements:
- Thorough knowledge of microprocessor or SOC design with 2+ years of direct work experience in one or more of the following areas:
- High performance cache controllers - pipeline design, hazard detection, parity/ECC generation, coherency policies, replacement policies
- Coherent on-chip Fabrics for high performance SOCs and design of associated control structures
- Knowledge of SystemVerilog
- Experience with simulators and waveform debugging tools
- Knowledge of logic design principles along with timing and power implications
- Understanding of low power microarchitecture techniques
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Experience in C or C++ programming
Education and Experience
PhD, master s degree or bachelor s Degree in technical subject area.
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