ASIC Engineer, Formal Verification

  • Sunnyvale, CA
  • Posted 2 days ago | Updated 1 day ago

Overview

On Site
$70 - $90
Contract - W2
Contract - 12 Month(s)

Skills

C++
Formal verification
VC-formal
JasperGold
power
SystemVerilog
Perl

Job Details

Requirements:

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
  • 5+ years of experience in Formal Verification
  • Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc
  • Proven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniques
  • Proven analytical skills to craft Client solutions to tackle industry-level complex designs
  • Demonstrated experience with effective collaboration with cross functional teams
  • Fluency in hardware description languages, such as SystemVerilog and SVA
  • Proficiency in scripting languages such as Python, Perl, or Tcl
  • Experience with JasperGold or VC-Formal
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