Overview
Hybrid
$80 - $90
Contract - W2
Contract - 12 Month(s)
Skills
Verilog
SystemVerilog
C/C++
UVM
verification
Job Details
- 3+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.
- 3+ years' experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
- Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.
Preferred Qualifications
- Experience in development of UVM based verification environments from scratch.
- Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.
- Experience with revision control systems like Mercurial(Hg), Git or SVN.
- Experience with low power design.
- Experience working across and building relationships with cross-functional design, model and emulation teams.
- Track record of 'first-pass success' in ASIC development cycles.
Bachelor's degree in computer science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining
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