Overview
On Site
$180,000 - $200,000
Full Time
Skills
PDKs
PCELLs
DRC
LVS
VSR
EMIR
Python
Design
Job Details
Sr. Staff IC CAD Engineer
San Jose, California
Full time
Duties and Responsibilities
- Develops and maintains PDKs.
- Supports all IC design CAD tools such as Cadence schematic entry, mixed mode circuit simulation, layout design, layout verification, logic synthesis, place & route, SKILL code development and developing custom Mentor Calibre DRC/LVS/xRC runsets for in-house proprietary processes.
- Performs software installation, license management, user support and vendor interface.
- Works with IC layout designers providing support for taping out physical designs and support device engineers developing PCELLs and power device layouts.
Requirements
- Bachelor's degree in Electrical Engineering, Electronics Engineering or Computer Science
- 12 years of experience (10 years if with master's degree)
- PCELLs development
- PDK development for in-house processes
- Development of DRC/LVS/xRC runsets
- Intimate knowledge of Caliber LVS, DRC and RCX menus and capabilities
- Proficiency in Skill and/or other scripting languages
- Experience with Encounter P&R
- Experience with Cadence VSR & EMIR
- Understanding Semiconductor Process Flow
- In-house CAD Support for worldwide Design Centers
- Excellent communication ability
- Familiarity with Perl and/or Python programming
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