Analog High-Speed Design Engineer (TSMC N3)

Job Summary

We are seeking a highly experienced Analog High-Speed Design Engineer with hands-on TSMC N3 (3nm) FinFET experience to architect, design, and validate next-generation high-speed analog and mixed-signal IP. This role focuses on advanced SerDes, clocking, PHYs, and high-speed I/O circuits in ultra-advanced process nodes, working closely with layout, verification, and system teams.

Key Responsibilities

• Design and lead development of high-speed analog and mixed-signal circuits in TSMC N3 FinFET technology
• Architect and implement:
• High-speed SerDes / PHYs (PCIe, Ethernet, USB, MIPI, etc.)
• Clocking circuits (PLLs, DLLs, CDRs)
• TX/RX front-ends, equalization, termination, and biasing circuits
• Perform schematic design, simulation, and optimization using advanced EDA tools
• Drive power, performance, and signal integrity optimization at 3nm
• Collaborate with layout engineers to ensure:
• DFM, DRC/LVS closure
• Parasitic-aware design (post-layout signoff)
• Work with foundry PDKs, TSMC N3 design rules, and reliability constraints
• Lead silicon bring-up, lab debug, characterization, and yield improvement
• Support cross-functional teams: digital, package, SI/PI, test, and product engineering
• Mentor junior engineers and contribute to design methodology improvements

Required Qualifications

• BSEE / MSEE / PhD in Electrical Engineering or related field
• 8+ years of analog or mixed-signal IC design experience
• Direct hands-on experience with TSMC N3 (or N5/N4 with N3 tape-out exposure)
• Strong expertise in:
• High-speed analog design (multi-GHz)
• FinFET device behavior and variability
• Noise, jitter, skew, and SI/PI analysis
• Proven tape-out success in advanced nodes ( 5nm)
• Proficiency with EDA tools such as:
• Cadence Virtuoso / Spectre / ADE
• EM/IR and parasitic extraction tools
• Solid understanding of:
• Device reliability (BTI, HCI, EM)
• Process corners and Monte Carlo analysis

Preferred Qualifications

• Prior ownership of production SerDes or PHY IP
• Experience with chiplet or advanced packaging (CoWoS, InFO, 2.5D/3D)
• Familiarity with system-level signal integrity and package modeling
• Foundry interface experience with TSMC (PDK reviews, signoff, yield learning)
• Experience in AI/HPC, networking, or data-center silicon

Soft Skills

• Strong technical leadership and ownership mindset
• Ability to work across global, cross-disciplinary teams
• Clear communication of complex analog tradeoffs
• Comfortable operating in ambiguous, cutting-edge environments