Performance Modeling/Verification Engineer - Remote

Title: Performance Modeling/Verification Engineer - Remote

Mandatory skills:

• SystemC,
• Transaction-Level Modeling, TLM concepts, Transaction-Level Modeling implementation,
• performance modeling, architecture exploration,
• C++ integration, C, C++ programming,
• verification methodologies, testbench creation, simulation,
• abstraction, behavioral, RTL, TLM, TLM2 models,
• memory controller architectures, DDR, LPDDR,
• UVM verification, AXI, AHB and bridges,
• version control systems, Perforce, Git,
• SV, UVM Functional, Performance Verification, Cycle approximate performance models,
• memory controllers, peripherals, interconnects, Identify bottlenecks, performance issues

Description:

JOB DUTIES:

• Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware.
• Collaborate with cross teams to integrate models into the client tools used for system-level designs, ensuring proper functionality and performance.
• Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.
• Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
• Create clear and comprehensive documentation for models, including usage guidelines and design specifications.

Deliverables:

• Cycle approximate performance models
• SV/UVM Functional and Performance Verification

EXPERIENCE AND EDUCATION:

• E/M.E/M.Tech or B.S/M.S in EE/CSE with over 5 years of recent hands-on experience in SystemC and TLM2 modeling
• Proficiency in C/C++ programming.
• Understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards is preferred.
• UVM verification experience is preferred.
• Experience with debuggers and handling complex projects.
• Experience working in geographically dispersed teams; must be a strong team player.
• Knowledge of system-level architecture including buses like AXI/AHB and bridges is a plus.
• Familiarity with version control systems such as Perforce or Git.

• Minimum 5 years of experience in SystemC.
• Recent and relevant experience with SystemC.
• Hands-on modeling projects using SystemC.
• Familiarity with Transaction-Level Modeling (TLM) concepts and implementation.
• Experience in performance modeling and architecture exploration using SystemC.
• Ability to work with C++ integration, since SystemC is built on C++.
• Exposure to verification methodologies in SystemC (e.g., testbench creation, simulation).
• Knowledge of modeling at different abstraction levels (e.g., behavioral, RTL, TLM).

VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.

Contact Details :

Account co-ordinator: Godwin D Antony Raj

VIVA USA INC.

3601 Algonquin Road, Suite 425

Rolling Meadows, IL 60008