Overview
Full Time
Skills
Innovation
Integrated Circuit
Management
Cross-functional Team
Emulation
RTL
System On A Chip
CPU
Physical Data Model
Verilog
VHDL
Logic Synthesis
Microprocessor
Power Management
Computer Hardware
Debugging
DFT
Scheduling
Communication
C
C++
Python
Perl
Job Details
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
Description As a CPU Debug and Power Management Microarchitect/RTL Engineer, you will own or contribute to the following: RTL ownership of CPU debug, trace, power management, clock management, and timer logic - development, assessment, and refinement of RTL design to target power, performance, area and timing goals Micro-architecture development and specification - Work with a cross-functional team of silicon and software experts to explore and define architectural features, develop micro-architectural details, and arrive at a detailed specification Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification Performance exploration and correlation - explore high performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance Design delivery - Aid in debug of issues at SoC level related to CPU power management, clock control, and debug features. Work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum Qualifications
Preferred Qualifications
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Description As a CPU Debug and Power Management Microarchitect/RTL Engineer, you will own or contribute to the following: RTL ownership of CPU debug, trace, power management, clock management, and timer logic - development, assessment, and refinement of RTL design to target power, performance, area and timing goals Micro-architecture development and specification - Work with a cross-functional team of silicon and software experts to explore and define architectural features, develop micro-architectural details, and arrive at a detailed specification Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification Performance exploration and correlation - explore high performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance Design delivery - Aid in debug of issues at SoC level related to CPU power management, clock control, and debug features. Work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum Qualifications
- Minimum BS and 3+ years of relevant industry experience
- Experience with Verilog or VHDL
- Experience with simulators and waveform debugging tools
- Experience with logic design with timing and power implications
Preferred Qualifications
- Knowledge and understanding of microprocessor architecture
- Expertise in one or more of the following areas: multiple clock/power domains and power management strategies, hardware debug and trace capabilities, DFT strategies, interrupt controllers, memory subsystem queuing, scheduling - starvation and deadlock avoidance, fabric communication protocols and interconnects
- SRAM design basics
- Understanding of low power microarchitecture techniques
- Understanding of high-performance design techniques and trade-offs
- Experience in C or C++ programming
- Experience using an interpretive language such as Python or Perl
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.