Overview
On Site
BASED ON EXPERIENCE
Contract - Independent
Contract - W2
Contract - 3+ mo(s)
Skills
SYSTEMVERILOG
UVM
SYSTEM VERILOG
MIXED SIGNAL VERIFICATION
DESIGN VERIFICATION
SIGNAL VERIFICATION
VMM
OVM
UVM
SILICON VERIFICATION
CHIP DESIGN
SOC
PRE-SILICON
POST-SILICON
PRE
POST
Job Details
Silicon Verification Engineer 2 Job Summary: Talent Software Services is in search of a Silicon Verification Engineer for a contract position in Redmond, WA. The opportunity will be three months with a strong chance for a long-term extension. Position Summary: The main function of this role is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans. Primary Responsibilities/Accountabilities:
- Define, document, and implement a UVM verification environment, including agents and scoreboards.
- Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral.
- Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
- Support post-silicon verification activities by collaborating with design and product teams.
Qualifications:
- Proficient in using Verilog and VMM/OVM/UVM.
- Experience in pre and post silicon verification test flow and automated test benches.
- Effective communication, collaboration, and teamwork skills.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field is preferred.
- 2-4 years of relevant experience required.
- Years of Experience Required: Minimum 2 years, ideally 3-6 years of overall experience in the field.
- Degrees or certifications: Not required but preferred.
- Best vs. Average: The ideal candidate would have previous experience with mixed signal exposure (analog and digital), be fluent with SystemVerilog and UVM, and have significant design verification experience.
- Performance Indicators: Performance will be assessed based on the completion of tasks within deadlines, and responding to team questions and communicating issues promptly.
- Minimum 2 years experience with SystemVerilog and UVM.
- Minimum 2 years experience with Mixed Signal Verification.
- Minimum 2 years experience with Design Verification Methodology.
If this job is a match for your background, we would be honored to receive your application!
Providing consulting opportunities to TALENTed people since 1987, we offer a host of opportunities including contract, contract to hire and permanent placement. Let's talk!
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