PSV DDR Validation Engineer

Position: PSV DDR Validation Engineer

Location: San Jose, CA

PSV DDR Validation Engineer

• Take lead responsibility for validating DDR memory subsystems (LPDDR4x, LPDDR5x) on multiple SoC platforms.
• Define comprehensive test plans and execute tests covering memory training procedures, performance benchmarks, stress scenarios, timing margin analysis, and overall reliability.
• Collaborate with design and firmware teams to develop, integrate, and debug firmware essential for memory training. Write necessary firmware components (like bootloaders, memory drivers, test hooks) to enable testing.
• Integrate and debug firmware for memory initialization and training, specifically on systems using RISC-V or ARM processors.
• Work closely with software and hardware teams to ensure firmware and hardware components interact correctly. Coordinate with board and Signal/Power Integrity (SI/PI) teams for related evaluations.
• Utilize standard lab equipment (oscilloscopes, logic analyzers, BERTs, power analyzers) for test execution, data collection, and troubleshooting memory-related issues. Perform root cause analysis for failures.
• Develop scripts (Python, Perl, C/C++) to automate test procedures and validation workflows.

Key skills - DDR, LPDDR4x, LPDDR5x, SOC, RISC-V, ARM, Python, Perl, C/C++), oscilloscopes, logic analyzers, BERTs, power analyzers, Lauterbach, JTAG, JEDEC LPDDR

B.E/M. E in Electronics & Communication Engineering

10 to 15 years of experience

• 10+ years of SOC validation experience
• At least 5 years of experience in post-silicon Memory subsystem validation, with a specific focus on LPDDR4x or LPDDR5 memory subsystems.
• Strong C/C++ programming skills, particularly for low-level code (like hardware abstraction layers) used in system bring-up. Proven experience integrating and debugging firmware in memory validation or general SoC environments.
• Deep understanding of DRAM operations, memory controller architecture, standard memory training algorithms, and JEDEC LPDDR standards (including timing parameters).
• Experience with silicon bring-up processes and associated tools like Lauterbach debuggers, JTAG interfaces, and trace analyzers.
• Familiarity with embedded operating systems and the typical boot sequences. System-level memory performance tuning and characterization.