Senior Mixed Signal Design Engineer


On Site
USD 112,000.00 - 218,400.00 per year
Full Time


Cross-functional team
Mixed-signal integrated circuit
Microsoft Office
Microsoft Azure
Artificial intelligence
Electrical engineering
Computer engineering
Computer science
Digital design
Volume testing
Physical data model
Test plans
Cloud computing
Computer hardware
Regulatory Compliance
Internal communications
Integrated circuit
System on a chip
Design for manufacturability

Job Details

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is driving Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Semi-custom and Central IP Silicon ( SCIPS ) team is instrumental in architecting, designing, and delivering industry leading silicon solutions to enable cutting - edge Microsoft cloud hardware for Artificial Intelligence , Compute , and Datacenter SoCs . We are looking for seasoned engineers with a dedicated passion for delivering differentiating silicon solutions for the next generation of Azure Cloud Silicon .

We are looking for a Senior Mixed Signal Design Engineer to join the team.

Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.


Required/Minimum Qualifications:

7+ years of related technical engineering experience

o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

7+ years of experience in a role that involves mixed-signal design.

5+ years of experience working with large cross-functional teams with diverse opinions.

6+ months of experience in High speed mixed-signal de sign.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:
  • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:
  • Demonstrated experience in design through volume production of highspeed links or similar mixed signal circuits in FinFET process.
  • Proficient with the latest mixed-signal - both analog and digital design flows and tools.
  • Ability to build VerilogA , Analog Behavioral Models.
  • Knowledge of Matlab, Simulink, Link Margin and Signal / Power Integrity requierments.
  • Experience with Silicon Photonics.
  • Understanding of Elector Static Discharge (ESD), advanced packaging.
  • Analyze and drive characterization and test data from lab and high-volume testing.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $112,000 - $218,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until June 20, 2024.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form .

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

#azurehwjobs #Cobalt #MAIA


  • Design and verification of low power mixed signal circuits such as receiver front-end, high-speed digital circuits, Digital Analog Converters (DAC) in cutting edge technology for use in highspeed links .
  • Work closely with system architect to develop innovative circuit solutions to meet various design criteria such as power, bandwidth, noise, linearity, jitter, mismatch etc.
  • Timing check analysis tools including for custom high-speed digital circuits and Mixed-signal verification of design.
  • Interface and collaborate with other physical design, Design for Test (DFT), Design verification and System on Chip (SoC) integration.
  • Supervise and optimize layout in latest Fin Fied-Effect Transistor (FET) technologies for volume production, check ElectroMigration (EMIR), Design For Manufacturer (DFM) etc.
  • Develop characterization and test plans and support bring-up, debug activities as needed.
  • Use knowledge of equalization techniques to optimize implementations.
  • Collaborate with cross functional team members with respect and with One Microsoft mentality to establish synergies.

Embody our Culture and Values