RTL Design Engineer

Please contact Abdul on "" OR email me at ""

• Develop RTL microarchitecture for ARM-based compute pipelines, DMA, and interconnects (AXI/AHB/APB).
• Integrate Cortex-M7, CoreSight, NIC, and other AMBA components into SoC architecture.
• Drive RTL design quality through synthesis, timing constraint development, Lint, and CDC checks.
• Set up and execute UVM-based verification and co-simulation with ARM CPU models.
• Work with multiple IP vendors to integrate memory controllers, peripherals (QSPI, UART, GPIO), and custom logic.
• Support system debug, early bring-up, and validation of SoC interfaces and compute fabrics.
• Experience with DRAM controllers, UCIe, or Compute-in-Memory architectures is highly valued.

What You Will Bring:

• 10+ years of RTL/microarchitecture experience in ARM-based SoCs, DSPs, or accelerators.
• Strong knowledge of AMBA protocols, CoreSight, and SoC debug infrastructure.
• Expertise in Verilog/SystemVerilog, synthesis, and timing closure.
• Hands-on experience with UVM, ARM co-simulation, and integration of complex IPs.
• Familiarity with high-speed I/O (UCIe, SerDes, Ethernet) and memory subsystems.

Please contact Abdul on "" OR email me at ""