FPGA Verification Engineer(Functional verification)

Job Title: FPGA Verification Engineer

Location: Mountain View, CA (On-site preferred; flexible work arrangements available)

Position Overview:

The FPGA Verification Engineer will play a key role in verifying and validating FPGA-based hardware designs to ensure functional correctness, performance, and reliability. This position requires deep technical expertise in SystemVerilog, UVM methodology, and industry-standard verification tools. The role involves close collaboration with design engineers to develop comprehensive test environments, drive coverage closure, and deliver robust verification solutions.

Key Responsibilities:

Develop, execute, and maintain FPGA verification environments using SystemVerilog and UVM methodology.

Collaborate with FPGA design teams to define test plans, develop testbench architectures, and identify corner-case scenarios.

Perform simulation-based verification using industry-standard tools such as QuestaSim and Synopsys VCS.

Conduct code coverage and functional coverage analysis to ensure verification completeness.

Develop automation scripts using Python or Perl to support regression testing and coverage collection.

Debug simulation failures, identify root causes, and communicate findings effectively to the design and validation teams.

Maintain high-quality verification documentation including test plans, reports, and coverage metrics.

Work cross-functionally with system architects and software teams to support FPGA bring-up and system-level validation.

Required Technical Expertise:

Strong understanding of FPGA design principles, architectures, and development flows.

Hands-on experience with SystemVerilog, UVM, and assertion-based verification.

Proficiency with verification tools such as QuestaSim, Synopsys VCS, or similar simulators.

Experience with scripting languages (Python, Perl, or Tcl) for test automation.

Familiarity with hardware description languages such as Verilog and VHDL.

Knowledge of coverage-driven verification and constrained random testing.

Excellent debugging, problem-solving, and analytical skills.

Preferred (Not Required):

Experience with FPGA toolchains such as Xilinx Vivado, Intel Quartus, or Synplify.

Familiarity with interface protocols (AXI, PCIe, DDR, Ethernet).

Exposure to formal verification, emulation, or hardware prototyping.

Experience with continuous integration and version control systems (Git, Jenkins, etc.).

Qualifications:

Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related field.

Proven experience in FPGA verification and testbench development.

Strong communication and teamwork skills with the ability to collaborate across hardware and software domains.

Demonstrated ability to meet verification goals and deliver results in a fast-paced engineering environment.