Senior ASIC Design Engineer

Overview

Accepts corp to corp applications
Contract - 19 day((s))

Skills

RTL design
ASIC Design
HAPS flow

Job Details

Hi,

Hope you are doing good!!!

Position: Senior ASIC Design Engineer

Location: San Jose, CA (Complete onsite) locals highly preferred
Duration: 6-12 months

Experience: 8+ years (Relevant)

A bachelor's degree in electrical or computer engineering, accompanied by a minimum of 10 years of experience in ASIC or a related field, or a master's degree in electrical or computer engineering with at least 8 years of experience in ASIC or a related discipline.

A comprehensive understanding of FPGA design, with proven expertise in partitioning multi-million gate designs across multiple FPGAs.

Demonstrated experience in RTL coding using Verilog/System Verilog and integration of third-party IPs

Our expectation is that candidate is proficient with the entire HAPS flow not just limited to building images

Having the experience to setup HAPS systems and triage issues around HAPS bringup is must for this position

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