Overview
Remote
Depends on Experience
Contract - W2
Contract - Independent
Contract - 6 Month(s)
Skills
FPGA
Job Details
Remote from PST timezone
Must have high speed Ethernet/packet processing/MACSec FPGA design experience.
RTL Design Engineers with deep expertise in high-speed Ethernet networking domain, with exposure in Layer2/Layer3(L2/L3) packet processing. You will work closely with the customer to develop cutting-edge network security solutions on FPGA based platforms.
- Strong RTL architecting and design skills in Verilog/SystemVerilog with expert knowledge of networking and wireline Ethernet packet processing
- Proficient in OSI model and L2/L3 protocols for RTL implementation on FPGA
- Solid understanding of networking domain control and data planes
- Familiarity with verification methodologies desirable (UVM/SystemVerilog preferred)
- Expertise in FPGA design flow including synthesis, implementation, STA and timing closure
- Exposure in AMD and Altera tool flows Versal device exposure is highly desired
- Good debugging skills and ability to analyze RTL and simulation mismatches
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