RF Layout Engineer

Job Description:
In this role, you will focus on the physical implementation and optimization of integrated circuits (ICs).
Responsible for creating and refining the physical layout of circuits, ensuring manufacturability, performance, and cost-effectiveness.

Responsibilities:
Physical Layout Design: Designing and implementing the physical layout of ICs, including placement, routing, and signal integrity analysis.
Design Optimization: Optimizing the physical design for performance, power consumption, and area.
Collaboration: Collaborating with cross-functional teams (e.g., design, simulation, process engineers) to ensure design meets requirements.
Simulation and Verification: Performing simulations to verify design performance, including timing, power, and signal integrity.
Documentation: Creating and maintaining design documentation, including schematics, layouts, and simulation results.
Design Flow Management: Utilizing and maintaining layout tools and design flow processes.
Troubleshooting and Debugging: Identifying and resolving design-related issues.
Staying Updated: Keeping abreast of the latest developments and innovations in physical design.

Minimum Qualifications:
Bachelor's degree (Master's preferred) in Electrical Engineering, or related fields.
Analog, mixed signal and/or RF layout experience is required
Experience performing layout of SERDES PHY, PLL, DDR PHY and RF transceivers
Experience working with advanced process nodes ( CMOS FinFET at 7nm and below)
Collaborating closely with circuit designers on block-level and top-level floor planning.
Experience with techniques such as RF shielding, high frequency routing, isolation concepts, and crosstalk mitigation
Generating intricate, transistor-level layouts for RF and analog circuit blocks.
This includes components such as LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
Extremely familiar with EDA tools: Cadence Virtuoso, Siemens Calibre, Innovus, Synopsis Custom Compiler and/or Silvaco Expert
Highly proficient with DRC/LVS/ERC/PEX, formal verification and timing analysis