Senior Design Verification Engineer - Ethernet PHY/PCS

  • Santa Clara, CA
  • Posted 60+ days ago | Updated 21 days ago

Overview

On Site
$180,000 - $200,000
Accepts corp to corp applications
Contract - W2
Contract - 6 Month(s)
No Travel Required

Skills

Ethernet
PHY
PCS
UVM
SystemVerilog

Job Details

Job Title: Senior Design Verification Engineer - Ethernet PHY/PCS
Location: Santa Clara, CA
Job Type: Contract, Full-time
Experience: 7+ years
We're seeking an experienced Senior Design Verification Engineer with expertise in Ethernet PHY or PCS to join our team in Santa Clara, CA.

Responsibilities:
- Develop and execute verification plans for Ethernet PHY or PCS
- Create and maintain testbenches and test suites
- Collaborate with design engineers to resolve verification issues
- Strong understanding of Ethernet protocols and standards

Requirements:
- 7+ years of experience in Design Verification of Ethernet PHY or PCS
- Strong experience in PM (Protocol Manager)
- Proven expertise in verification methodologies (SystemVerilog, UVM)
- Excellent problem-solving skills and attention to detail

What We Offer:
- Competitive hourly rate
- Opportunity to work with a leading company in the industry
- Collaborative and dynamic work environment

If You're Interested:
Please send me a message or comment below with your resume and a brief introduction.

#DesignVerification #EthernetPHY #PCS #JobOpening #CareerOpportunity #SantaClara #CA

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