Design Verification Engineer (DDR)

Hi,

Hope you re doing well.

We are currently hiring Design Verification Engineers (DDR IP or SoC Level) for our client. This is a U.S. remote role with excellent compensation and growth potential. Please find the details below:

Position: Design Verification Engineer DDR (IP/SoC Level)
Location: U.S. Remote

Key Responsibilities:

• Define and implement verification strategies and test plans for DDR memory interface designs.
• Develop UVM/System Verilog-based testbenches and reusable verification components.
• Perform protocol-level verification for DDR memory interfaces and validate compliance with JEDEC standards.
• Collaborate with architecture, RTL, and system teams to address design intent and corner cases.
• Manage functional coverage, regression setup, and closure.
• Integrate DDR models, controllers, and PHYs while validating interactions.
• Debug and resolve simulation failures and functional issues.
• Drive code and functional coverage improvements to ensure high-quality verification.
• Participate in technical reviews and mentor junior engineers.

Required Skills:

• 10+ years of experience in ASIC/IP/SoC verification.
• Strong expertise in System Verilog, UVM, and functional coverage methodologies.
• Hands-on experience with DDR3, DDR4, DDR5, and LPDDR protocols.
• Familiarity with DDR controllers, PHY integration, and JEDEC compliance.
• Proficient in Synopsys VCS, Cadence Xcelium, Quest Asim, or similar tools.
• Scripting skills in Python, Perl, or Shell for automation and regression management.
• Solid debugging and problem-solving skills.
• Knowledge of AXI/AHB protocols and interconnects is a plus.
• Experience working with memory models and timing analysis.

Preferred Qualifications:

• Post-silicon validation or DDR hardware bring-up experience.
• Familiarity with formal verification tools.
• Experience with low-power verification and timing closure tools.