Overview
On Site
Accepts corp to corp applications
Contract - Independent
Contract - W2
Contract - Full-Time
Skills
RTL
System Verilog
UVM
Job Details
Job Title: Design Verification Engineer
Location: Sunnyvale CA /Redmond WA/ Austin TX(Hybrid)
Duration: Full-Time Only
Job Description:-
- Strong understanding of SV and UVM and good debugging skills.
- Understanding of AMBA protocols.
- Understand design specs and develop test plans based on functional and architectural requirements
- Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing
- Develop directed and random testcases, perform coverage analysis, and close functional/code coverage
- Debug simulation failures and work closely with RTL designers to resolve issues
- Execute regression runs, analyze results, and contribute to continuous improvements
- Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed
- Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains
- Document test environments, test plans, and results for internal and external reviews
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