Overview
On Site
$CAD $76.44-89.72 / hr
Contract - W2
Contract - to 07/07/2026
Skills
Design Verification Engineer
Job Details
Job Description:
Responsibilities:
- Develop/Maintain tests for functional verification with UVM verification at the subsystem level.
- Build test bench components to support the next generation IP.
- Maintain or improve current test libraries to support IP level testing.
- Technically lead IPs in Control Fabric.
- Have exposure to AXI protocol and Boot code Verification.
- Provide technical support to other teams.
- 5+ years' experience required.
- Good at C/C++.
- Good at SV and UVM.
- Good scripting knowledge in Perl, Ruby and Make file.
- Familiarity with System Verilog and modern verification libraries like UVM.
- Bachelors (required) or Masters degree in computer engineering/Electrical Engineering.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.