Verification Engineer - Intermediate (US)

JOB DUTIES:

Participate in design and functional verification of a block(s) of IP. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block and overall system. Be responsible for developing and improving simulation test environments consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally and work within the existing verification infrastructure. Be familiar with hardware modeling and/or assertion-based verification methods.

In this role you will be part of a PCIe development and productization team. A majority of the verification will target PCIe device testing DMA, CXL, IDE, VIP models, traffic generators/checkers, etc.

EXPERIENCE:

- 8 or more years of proven verification experience on Verilog and System Verilog for IP development and verification required

- Familiar with UVM verification methodologies and environments

- Strong debug skills

- Experience with simulation tools ModelSim/VCS and VIPs

- Experience in Verilog/SystemVerilog

- Strong analytical skills and attention to detail

- Excellent written and communication skills

- Familiarity with PCIe and serial protocols is a bonus

- AMD/Xilinx FPGA and tools experience is a bonus

Essential skills: RTL verification experience, Verilog/System Verilog, Modelsim/VCS, UVM

Nice-to-have skills: FPGA Experience (Xilinx/AMD FPGA preferred), Vivado experience