VLSI CAD Engineer

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Description APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Provide static timing analysis methodology to customer VLSI design team. Help design team resolve the STA tool issues. Implement Perl and Python to help design team for enhancing the tools and improving the effectiveness. Implement flows to verify transistor level circuits in the areas of timing. Support tools to testify transistor level circuits in the areas of signal integrity. Work closely with digital and analog IC designers to ensure the design to meet functionality, timing, electrical, power, and signal integrity goals. Drive EDA vendors to meet the need of Apple innovative design. Develop and maintain the specific workflows, scripts, and methods used for analyzing timing at transistor level circuits. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field.
• Experience and/or education must include:
• Experience in CMOS circuits at the transistor level to understand customer's needs.
• Experience in EDA tools for better use tools, and experience interacting with vendors.
• Experience in coding, including experience processing data and controlling vendor tools in internal flows.
• Using Perl or Python, including experience creating & maintaining internal flows.
• Understanding Static Timing Analysis (STA) to close timing for high-quality chip tape-outs.
• Experience in Dynamic simulation with tools like hspice to confirm STA results.
• Experience in power optimization for digital circuits in sub-micron process technology.
• Experience in Verilog and/or HDL language to define RTL circuit behaviors.

Preferred Qualifications

• N/A

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