DFT Engineer

Overview

Remote
Depends on Experience
Contract - W2
Contract - 12 Month(s)
No Travel Required

Skills

ASIC
Cadence
DFT

Job Details

We are looking for an experienced DFT Engineer to join an ASIC Design Team on a 1-year contract. You will be responsible for ensuring testability throughout the ASIC design process while collaborating with cross-functional teams.

Responsibilities:

  • Lead DFT efforts in ASIC designs using VHDL, Verilog, or System Verilog.

  • Follow company ASIC development process and implement DFT methodologies.

  • Work with Cadence/ Mentor ATPG tools, hierarchical scan testing, JTAG, and memory/logic BIST.

  • Collaborate with test engineers to implement and debug test patterns.

Basic Qualifications:

  • Bachelor s degree in Electrical/Computer Engineering (8+ years of experience) or Master s degree (6+ years).

  • Experience in full product life cycle of ASIC design and test pattern generation.

  • Proficient in HDL (VHDL/Verilog/System Verilog) and Tcl, Python, or Perl.

  • Experience with Cadence/ Mentor tools, IEEE standards, and test insertion.

Preferred Qualifications:

  • Master s Degree in Electrical/Computer Engineering.

  • Expertise with Cadence Modus DFT tools.

  • Knowledge of Synthesis, P&R, and Static Timing Analysis.

This is a 1-year contract role offering the chance to work with advanced technologies and a collaborative team environment.

**Must be able to work for any employer without sponsorship.
**Must be able to obtain Security Clearance.
 
 
 
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