ASIC Verification (Fulltime)

Job Description

• Work with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level.
• Engage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development.
• esponsible for creating tests to verify the SOC design at the system or block level and to implement checking mechanisms to ensure coverage closure.

Job Requirements

• 15+ years (BSEE), 12+ years (MSEE), or 8+ years (PhD) of relevant industry experience
• Expertise in developing testbenches using System Verilog and UVM
• Experience using directed and constrained-random test methodologies, coverage closure and gate-level simulations
• Strong object-oriented programming knowledge using SystemVerilog
• Strong problem-solving and debug skills capable of isolating problems to the block level
• Experience extracting detailed test requirements from complex system and block specifications
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience in the use of scripts to support automation (Python, Make, Csh, Bash, Tcl, etc)
• Familiarity with C-code/embedded firmware/debuggers
• Creating and managing team commitments, schedules, milestones, and deliverables
• Ability to work in a dynamic environment with changing needs and requirements
• Ability to be a technical anchor and mentor for team members
• Ideally you are also experienced in:
• Using Formal verification methods and tools like Jasper Gold.
• Real-time data processing systems
• Audio signal processing
• Audio performance concepts (SNR, THD, SINAD, DR, etc.)
• Familiarity with standard interfaces (SPI, I2S, PDM, PWM, USB, etc.)
• Familiarity with wireless protocols (Wi-Fi, BLE, BT, MAC/PHY)
• Familiarity with wireless different processors (ARM, HiFi, RISC-V)
• FPGA hardware emulation