Design Verification Engineer 504792

Overview

On Site
USD 70.00 - 75.00 per hour
Contract - W2

Skills

Durable Skills
SystemVerilog
Test Cases
UVM
Debugging
Test Plans
Collaboration
Communication
Conflict Resolution
Problem Solving

Job Details

Job Description

ONSITE 5 days - San Jose, CA or Austin, TX

MUST

Design Verification experience: 3+ year experience if in Austin; 5+ year experience if in San Jose, CA
SystemVerilog (developed test benches and test cases)
UVM
Debug
Verification test plans (develop and execute)

Essential Skills & Qualifications:

SystemVerilog: proficient in SystemVerilog for developing testbenches and test cases,
UVM: solid understanding and practical experience with UVM (Universal Verification Methodology)
Debugging: strong debugging skills to identify and resolve functional failures
Verification Planning: experience in developing and executing verification test plans
Collaboration: Ability to work effectively in a team environment
Communication: strong verbal and written communication skills
Problem-Solving: Ability to independently solve complex problems and proposed solutions
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