Overview
On Site
$$70 - $80/hr
Accepts corp to corp applications
Contract - W2
Contract - Independent
Skills
Palo Alto
Integrated Circuit
Debugging
Intellectual Property
IP
Static Timing Analysis
Timing Closure
RTL
Job Details
Job Description:
- Full chip and Block constraints development and constraints generation.
- Full chip and Block Synthesis, STA, and timing closure using Primetime and DMSA flow
- Run and debug Formality and VCLP Tools
- Interfacing with internal and external teams, including Design, IP, Library
- Methodology & Flow development of Synthesis, Formality, STA & Timing Closure
- Working independently with the PNR & RTL design team on Physical implementation and Power-intent requirements.
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