Board/System-level Power Integrity Engineer

Title: Board/System-level Power Integrity Engineer

Location: Onsite in Santa Clara, CA 4 days minimum

Length of Contract: 6 months+ extension.

Background Check Required

Need: Hiring manager built a new group 2 years ago, compiled of power design and verification resources. This team validates their board from a power distribution and power integrity standpoint, but is mainly comprised of design engineers as such these folks are more heavily focused on the digital design aspects of the job and less on the DC-DC Power Distribution and Power Tree Analysis. The folks are mainly designers and aren t as savvy at understanding and interpreting the power tree portion and making recommendations, etc. They currently have one full-time engineer who has been designing load power slammers to test the transient response of the power converters, however he is only able to do partial duty here. They need a dedicated resource to review the designs and draw out the power tree, do the analysis and testing, and measure the DC-DC conversion to make sure the power is clean and they aren t losing power, etc.

Initially had 2 full-time engineers, one of whom was doing more of the testing piece (senior-level), however this person is on a leave of absence. Hence, urgency is borne of filling in this gap to cover while that person is out, and when that individual returns they will most likely settle back into more of a Component Engineering role.

Scope:

As a Senior System/Board-level) Power Integrity Engineer, the candidate will collaborate with cross functional HW and design teams around the organization. Candidate will contribute to the development of cutting-edge switch networking products, working from concept through bench validation. Candidate s role will be critical in ensuring the power delivery system for the products is optimized for performance, reliability, and scalability.

Note: This is All at the Systems/Board Level Client buys an IC off the shelf from BROADCOM and the goal here is to integrate this onto their board and design their power distribution mechanism around this IC. They are building the board with an interposer and slammer on there and simulate the power drop that the IC would do. This involves doing the power analysis, probing the board, etc. Client uses external Power Supplies PSUs that take the 110 or 220 or 440 Volts etc. and drop it down to 12 Volts. This is purely focused on the DC to DC conversion. Candidate needs to have background and understanding in Microcontrollers, LDOs, DPMs, Discreets and Passives, everything around the Power Distribution aspect of supporting an IC from Broadcom, etc.

Duties/Responsibilities:

• Power Integrity Analysis: Perform power integrity analysis and mitigation for ASIC designs, ensuring robust power delivery throughout the product lifecycle.
• Collaboration with Design Teams: Work closely with hardware and design teams to define power delivery strategies, ensuring alignment with overall system requirements.
• Power Validation & Measurement: Use advanced lab equipment to validate power integrity, including oscilloscopes, DMMs, DC loads, and Bode plots.
• Optimization of Power Delivery: Design and optimize power delivery systems, including power trees and decoupling strategies, to meet performance and stability goals.
• Schematic & Layout Review: Review and provide feedback on schematics and layouts using Cadence tools to ensure optimal power distribution and integrity in the final design.
• Vendor Interaction: Collaborate with external vendors to align on design requirements and help debug power integrity issues.
• Advanced Power Technologies: Apply deep knowledge of DC-DC power technologies, control modes (current mode, voltage mode, constant-on-time), and multiphase architectures to address power challenges.
• Troubleshooting & Debugging: Use advanced problem-solving skills to troubleshoot and resolve power-related issues in both design and lab environments.
• Documentation & Reporting: Document power integrity analyses, design decisions, and test results, and present findings to cross-functional teams.

Qualifications/Necessary Skills:

• Experience: 5+ years of experience in power integrity engineering, with a focus on high-performance computing or networking hardware.
• Education: BSEE, MSEE, or equivalent experience in Electrical Engineering or a related field.
• Proven experience in analyzing, mitigating, and optimizing power integrity for ASIC or FPGA designs, including detailed troubleshooting in the lab.
• Proficiency with lab equipment (oscilloscope, DMM, DC load, Bode plots) and experience with power measurement techniques.
• Solid understanding of control theory, including gain margin, phase margin, stability, and related metrics for power integrity analysis.
• In-depth understanding of DC-DC power converters, multiphase architectures, and various control modes (current mode, voltage mode, constant-on-time).
• Experience reviewing schematics and layouts, specifically with Cadence tools for ASIC design.

Nice To Have:

• Knowledge of Python for automation and data analysis is a plus.