Principal RTL/Security Architect (ARMv8-A)

We are seeking a Principal RTL Architect with 15+ years of experience in system architecture and micro-architecture definition, specifically for high-performance ARM SoCs. This role requires expertise across core integration, cache coherency, and the hardware-software interface for security.

Essential Qualifications:

Experience: 15+ years of technical leadership in digital ASIC design and complex SoC architecture.

Core Expertise: Deep, hands-on experience integrating and optimizing ARM Cortex-A78/A72 CPU cores.

Coherency: Expert knowledge of multi-core coherency protocols, including CCI/CCIX/CMN and AMBA ACE/CHI.

Security Architecture: Expert understanding of the ARMv8-A Architecture (AArch64, Exception Levels: EL0-EL3) and the TrustZone security model.

Secure Monitor Mode (SMM): Proven ability to define the hardware interface, design, and integration logic for the highest privilege level, specifically the Secure Monitor (EL3), which manages transitions between secure and non-secure worlds.

PPA: Demonstrated ability to drive micro-architecture trade-offs to meet aggressive Power, Performance, and Area (PPA) targets.

RTL: Fluency in SystemVerilog/Verilog, with expertise in formal verification, CDC, and low-power techniques.

Highly Desired:

Prior experience defining or reviewing the architecture of hardware components dedicated to security, cryptography, or memory protection.

Experience with embedded/real-time architectures like the ARM Cortex-R/E series.

Experience collaborating closely with firmware and boot-ROM teams on initial platform bring-up.