About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your ImpactThe Analog Mixed-Signal Optical PHY (AMS-OPHY) Central Engineering unit delivers 10G-800G high-speed optical and electrical connectivity solutions to OEM's for the networking and telecommunication markets. It's PAM4-DSP based transceivers deliver a first-in class solution to present and future data throughput demands across multiple applications. Common applications for the AMS-OPHY products include long haul and metro, inter and intra-data center interconnects and 5G.
What You Can Expect- High speed analog to digital (ADC) or digital to analog (DAC) interface circuits
- High speed ADC or DAC driver circuits
- High speed clock conditioning circuits
- Auxiliary circuits (i.e., biasing, reference generation)
- Behavioral modeling to aid/facilitate the circuit design process
- Calibration algorithms to mitigate circuit non-idealities
- Model analysis/development for characterizing the impact of circuit performance at the system level
What We're Looking ForMinimum Qualifications:
- Candidate MUST be currently pursuing an MS/PhD (preferred) degree in EE or related technical field(s)
- Candidate MUST have a deep and comprehensive understanding of analog integrated circuit fundamentals
- Candidate MUST have a good understanding of signal processing fundamentals
- Candidate MUST have experience with CAD tools and simulators such as Cadence Virtuoso and Spectre
Preferred Qualifications:
- Research or Major design project experience in data conversion (i.e., ADC's & DAC's) interfaces
- Research or Major design project experience in high-speed analog front ends (i.e., CTLE's, VGA's, TAH/SAH's)
- Research or Major design project experience in clock conditioning circuits (i.e., PLL's, DLL's, PI's)
- Experience in behavioral modeling in Verilog-A and or System Verilog
- Experience in C, Python and Matlab programming/modeling in a Unix type environment
Expected Base Pay Range (USD)31 - 61, $ per hour.
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage, perks and discount programs, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
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