Signal Integrity (SI) Engineer

Overview

On Site
Depends on Experience
Accepts corp to corp applications
Contract - Independent
Contract - W2
Contract - 12 Month(s)

Skills

PCB
Collaboration
Conflict Resolution
HFSS
Interfaces
JEDEC
Layout
Modeling
PCI Express
Problem Solving
Art
Clarity
Regulatory Compliance
Signal Integrity
LPDDR
Gen7

Job Details

Role Signal Integrity (SI) Engineer

Location: San Jose, CA (Onsite)

Experienced (>5y) Signal Integrity Engineer to support high-speed interface development and
validation. The engineer will work on state-of-the-art technologies such as LPDDR5X, PCIe
Gen7, and UCIe (64G).
Responsibilities:
Perform channel modeling, extractions, and eye analysis for high-speed interfaces.
Conduct pre- and post-layout simulations to ensure compliance with interface standards.
Analyze crosstalk, reflections, jitter, and insertion/return loss.
Collaborate with design, package, and PCB teams to optimize SI performance.
Generate reports and recommendations to support design decisions.
Qualifications:
Strong background in signal integrity for high-speed serial and memory interfaces.
Hands-on experience with
o HFSS or Clarity, Siwave or PowerSI,
o SystemSI or ADS or AEDT
Familiarity with JEDEC/LPDDR5/6 and PCIe/UCIe standards.
Strong problem-solving skills and ability to work across cross-functional teams.

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