Memory PHY RTL design Engineer

Overview

$$60-$65/hr on W-2
Contract - W2
Contract - 12 month(s)

Skills

Mergers and Acquisitions
Firmware Development
IO
Intellectual Property
IP
IPS
Collaboration
Computer Hardware
ROOT
DV
Digital Design
Debugging
Firmware
UVM
Linux
Microsoft Windows
C
C++
Verilog
SystemVerilog
Scripting Language
Python
Perl
Tcl
Change Data Capture
SERDES
DDR SDRAM
Organizational Architecture
Mixed-signal Integrated Circuit
RTL
Computer Engineering
Electrical Engineering

Job Details

Role: Memory PHY RTL design Engineer

Location: Boxborough MA 01719 | Hybrid 3 days onsite per week

Duration: 12+ months

THE ROLE:

The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

Key Responsibilities:

  • RTL design for memory I/O
  • PHY Digital Architecture development from pathfinding, coding, verification to physical implementation
  • PHY link layer design, implementation & verification with Analog and System architect.
  • PHY Analog/Digital co-design
  • Digital design and RTL coding
  • Timing Synthesis & Drive Physical implementation
  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Build the unit tests
  • Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues

Preferred Experience:

  • Digital design engineering experience
  • Proficient in debugging firmware and RTL code using simulation tools
  • Proficient in using UVM testbenches and working in Linux and Windows environments
  • Experienced with Verilog, System Verilog, C, and C++
  • Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus
  • Knowledge of clocking architectures, synchronization, and CDC methodology
  • SERDES, DDR, Memory Controller, or MAC Design experience is preferred
  • Strong understanding of computer organization/architecture.
  • Mixed signal RTL experience is a plus

Academic Credentials: Bachelors or Master's degree in computer engineering/Electrical Engineering.

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