Overview
Skills
Job Details
Hi,
Please check the job description as below and let me know you if you would be interested and available. Please let me know your available time for a quick call
Memory Controller Systems Architect
San Jose, CA
6+ Months
Responsibilities include, but not limited to:
Modeling and analysis of system cache, memory controller scheduling algorithms, and features
Develop tests, testplans and testing infrastructure for new architecture/features
Developing, evaluating and optimizing new memory/storage architectures that improve cost, performance, power and reliability of Mobile product portfolios
Part of team assisting development of Architecture for Memory/storage Controllers
FPGA/RTL design, validation for Memory/storage Controllers
Conduct in-depth analysis of product requirement dashboards, CPU and GPU benchmarks to identify memory bottlenecks and areas for improvement.
Demonstrates good understanding & conducts research on industry trends and innovations in memory subsystem to ensure solutions, deliverables are best in class
Build and develop performance and functional models and simulators
Build, develop, and evaluate interconnect and memory hierarchies for high-performance mobile memory architectures
Successful candidate for this position will have the following:
Must have a BS or Master's degree or PhD in Electrical and/or Computer Engineering or Computer Science
5+ years of experience in ASIC development, HW Systems for Wireless/Wireline SoCs
5+ years work experience in microprocessor, SoC, memory controller and/or interconnect IP design
Knowledge of DRAM specification (e.g., LPDDR4/5, DDR4/5) and of bus protocols (e.g., AMBA5 CHI, AMBA4 ACE or AXI)
Experience with Verilog or VHDL, coupled with design synthesis targeted to achieve specified frequency, power, and area targets
Experience with CPU or compute subsystem memory micro-architecture
Hands-on Experience in CPU, GPU, DDR ASIC or systems development
Hands-on Experience in Performance, power benchmarks for Mobile systems
Processor system knowledge including basic understanding of SoC systems as well as operating system software
Experience in ASIC or FPGA Design, Verification
Experience in Architecture, Microarchitecture of high speed, low power, optimal area IPs
Great communications skills with the ability to articulate results
Preferred Skills:
Mobile Platform SW or HW knowledge
Strong working knowledge of DRAM, NAND and other memory/storage devices
Working Knowledge of LPDDR3/4/5, UFS, eMMC, PCIe
Experience in C++, SystemC, Python, Octave or other System programming languages
Experience in Model Development (CPU, GPU, Memory)
Exposure to Custom HW platform development
Strong leadership skills and cross-functional teamwork
Self-motivated and significant problem-solving skills
Good understanding of QoS concepts
Good handle in Object oriented programming and general SW debug (C++)
Strong scripting skills (Perl/Python)
Experience with data analysis using Excel, R, Python etc.
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Thanks & Regards.
Isaac Rajiv
Kutir Corporation
Ph: