ASIC CAD/EDA Flow/Methodology Developer

Currently, we have an opening for ASIC CAD/EDA Flow/Methodology Developer with our Client in Santa Clara, CA. I appreciate your time and look forward to hearing from you.

Role: ASIC CAD/EDA Flow/Methodology Developer
Location: Irvine or San Jose, CA & Minneapolis, MN

Job Summary:
We are seeking a highly skilled ASIC CAD/EDA Flow/Methodology Developer with a strong background in analog/mixed-signal layout and advanced nodes (including FinFET technologies). The ideal candidate is experienced in developing and improving ASIC/SOC design methodologies, with solid programming skills and deep knowledge of CAD tools and flow.

Required Experience and Skills:

• 8+ years in analog/mixed-signal layout design with deep submicron CMOS circuits.
• 3+ years of recent experience with advanced nodes, including FinFET technologies.
• Strong understanding of ASIC/SOC CAD flows and methodologies.
• Proficient in programming with SKILL, Perl; Python is a strong plus.
• Solid fundamentals in software development and design automation.
• Familiarity with EMIR (RV) and physical design verification (DRC, LVS, PEX, ERC, waivers).
• Understanding of circuit design concepts: device characteristics, SPICE, Verilog netlists, simulations.
• Excellent communication and interpersonal skills.

Key Responsibilities:

• Influence tool development, design flows, and methodologies for design construction, signoff, and optimization using a data-driven approach.
• Drive signoff closure: timing (SI, OCV), power, IR, and physical verification at both block and chip levels.
• Perform block-level and full-chip integration.
• Interpret and resolve LVS, DRC, and ERC issues efficiently.
• Deliver high-quality layout meeting performance, area, and power constraints using advanced CAD tools.
• Implement timing closure techniques and signal integrity (SI) fixes.
• Utilize Synopsys (ICC/ICC2) and Cadence (Innovus, Virtuoso) tools.
• Develop design automation scripts; proficient with UNIX systems.